Senior Behavioral FrontEnd ASIC Engineer

  • Profesionales y Técnicos
  • Full time
  • 6 días -
  • Cañada

Información del trabajo

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    Remuneración EUR 0-5000 / Mes

Descripción del trabajo

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

R&D Expert Engineer

This position of “R&D Expert Engineer” is an ASIC Design, Implementation and Verification Engineer with experience in both back-end and front-end ASIC development flows whose mandate is to provide targeted support to mixed-signal High-Bandwidth Memory (HBM) and DDR PHY IP customers. The targeted customer support will include both pre-Sales and post-Sales support. Activities of customer support include such tasks as IP integration and implementation, design debug, silicon bring-up, and silicon testing. When not actively supporting customers, the candidate will participate in design, verification, silicon testing, documentation, or other related tasks as may be assigned by the Manager. The successful candidate will exercise skills in a variety of areas including but not limited to RTL coding, test bench and test case development, linting, synthesis, STA, place & route, silicon debug, and documentation. The emphasis for the current opening is “Front-End” activities including RTL development and Behavioral/GLS Verification related to our HBM and DDR PHY products. Experience with HBM or DDR protocols is a definite asset but not mandatory. This position requires extensive interaction with customers, including periodic international travel to assist customers at their sites.

Key Qualifications

BSEE degree or Applied Science degree (or equivalent) with 10+ years of related experience

Experience in ASIC RTL design and verification at the chip level and block level

Strong Verilog, system Verilog, PERL, and TCL skills

Strong synthesis and STA background

DFT/ATPG skills or experience are a significant asset

Excellent communication and presentation skills

Knowledge in silicon debugging

Previous knowledge in customer support

Must be able to travel periodically

Preferred Experience

Interact with and, in some instances, visit customers

Support HBM and DDR PHY integration, silicon bring-up, and silicon debug activities

Participate in the generation of data books, application notes, and white papers

Generate test benches and test cases

Perform RTL and gate-level SDF-annotated simulations

Perform constraint development and physical design activities

May perform mixed-mode (digital + analog) simulations

Assist test engineers with silicon evaluation

Develop and execute functional test/verification plans

Write synthesizable RTL code for circuit portions of integrated circuits

Other related duties as assigned by the manager

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected]

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